This invention relates generally to the field of integrated circuits, and more particularly to a system and method for distributing a reference clock in an integrated circuit.
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are formed in and on a substrate and are interconnected to form an integrated circuit. Typically, integrated circuits are attached to a lead frame and protectively packaged to form an integrated circuit chip that can be directly connected to a printed circuit board of an electronic device. Through the printed circuit board, the integrated circuit chip is connected to other chips and to external inputs and outputs.
Integrated circuit chips typically operate based on a reference clock signal received from the printed circuit board. On the chip, the reference clock is distributed to the various devices that utilize the signal. To reduce jitter of the reference clock, inverters have been used as part of the on-chip clock distribution system. For high frequency systems, however, jitter remains a problem.
The present invention provides a system and method for distributing a reference clock in an integrated circuit that reduces or eliminates at least some of the problems and disadvantages associated with previous systems and methods.
In accordance with one embodiment of the present invention, a clock distribution system and method for an integrated circuit includes a power supply line and a plurality of clock distribution elements. The power supply line is operable to provide resistive-capacitive (RC) filtered power. The clock distribution elements are coupled to the power supply line. The clock distribution elements are operable to be powered by the RC filtered power to distribute a reference clock signal.
More specifically, in accordance with a particular embodiment of the present invention, the clock distribution elements may each comprise at least one of a reference clock line, a repeater for the reference clock line and an output buffer of the reference clock line. In this and other embodiments, the RC filter may comprise a multi-stage filter. The multi-stage filter may include a first stage distributed RC filter and a second, single stage filter.
Technical advantages of the present invention include providing an improved method and system for distribution of a reference clock on an integrated circuit chip. In one embodiment, the clock distribution system is powered by a filtered and/or cleaned power supply signal to reduce noise. As a result, reference clock jitter across the distribution system remains low.
Another technical advantage of the present invention includes providing a multi-stage resistive-capacitive (RC) filter for an on-chip clock distribution system. In one embodiment, the RC filter is a two-stage filter with a distributed first stage. The multi-stage filter provides efficient noise attenuation and allows high-speed and distributed serial links on the integrated circuit.
Still another technical advantage of the present invention includes providing a modular design for a clock distribution system. In one embodiment, the clock distribution system comprises a number of modules each constructed from repeater, local buffer, wire and/or filter units. This design allows easy adaptation to various circuit layouts and configurations.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description and claims. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some, or none of the enumerated advantages.